A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs
نویسندگان
چکیده
منابع مشابه
Design and Implementation of Fast Locking and Harmonic Free in Multiphase Digital DLL – Robust to Process Variations
An ADMDLL(All Digital Multiphase Delay Locked Loop) with Harmonic free , Low power , Low Jitter and Immune to SSN features are presented. Harmonic Free and Immune to SSN of the proposed ADMDLL are achieved by implementing a Narrow-Wide Coarse Lock Detector (NWCLD) and Time to Digital Converter (TDC),which maintains the delay between reference clock and outgoing clock with in the suitable range ...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2017
ISSN: 1349-2543
DOI: 10.1587/elex.13.20161020